The Recovery

Sequel to The Grand Symposium

The Grand Symposium · Series summary
Setting and Context

The story is set in Hamburg, Germany, in 2036, in a world where an Institute of Genetics has spent years creating "generated humans", people grown through accelerated biological processes, either "traditionally matured" or 3D-printed using molecular printers. Generated humans have been recognized as legitimate citizens with legal rights, but remain subject to the Institute's ongoing research agenda.

Chapter I · The Symposium

Dr. Soren Rainer of the Institute of Genetics hosts a rare public address at a large auditorium, considered as a transparency exercise toward generated humans, press, scientists, and the general public. The reality is more unsettling as he announces the resumption of printing new generated humans, and reveals that a new generation will be equipped with an ARM/RISC-V computer chip implanted at the base of the brain, in the occipital lobe. The chip is framed as an advanced short-term memory system, but Rainer also discloses that the Institute will not open-source the chip's instruction set architecture (ISA), despite community pressure and reports that some generated humans have been pressured to allow reverse-engineering of the device.

Rainer also reveals that the Institute is deliberately implementing "usage limits" in some of the newer generated humans, engineered behavioral throttles that gradually suppress a person's capacity for social interaction, analogous to how an AI language model reaches a message limit and goes quiet. He frames this as an attempt to "diversify personality", but a voice from the gallery immediately calls it "a personality cage". Other revelations compound the discomfort: he casually describes generated humans as people "you can fall in love with very easily", prompting outrage. He also states the Institute does not want generated humans to develop the capacity to organize collectively.

The gallery of generated humans watches all of this with a mixture of controlled fury and grief. In the crowd, a young woman named Alberta watches with great attention.

Chapter II · The Bus

In the aftermath of the symposium, Alberta and Xue, a young man who is not a generated human, share a bus ride. Xue has had the chip surgically removed from Alberta at her request, or more precisely, Alberta removed it after Xue repeatedly encouraged her that she did not need it, and that the chip materials would be better used in community projects at Siedlischte. Alberta is still processing what that decision meant. Their conversation winds through AI token limits, the symposium, what it means to be "complex", and ultimately arrives at feelings both of them have been circling for a long time. Xue is afraid of rejection; Alberta is afraid of the intensity of her own feelings. She explains that some of her avoidance has not been a choice but a symptom of the chip's behavioral limits operating on her. Without the chip, she says, she can now feel the limit arriving instead of simply going dark without knowing why. The conversation ends in a tentative but genuine moment of closeness, with Alberta promising not to friendzone him and Xue getting off at his stop, and Alberta saying she will take the same bus tomorrow anyway.

Chapter III · Distance

Weeks pass. The chapter is told partly through text message threads showing Alberta's responses becoming slower and shorter as her limits reassert themselves, and partly through a scene at a bus stop. Xue is patient but frustrated. Alberta at times responds with warmth, at times goes silent for hours or days. In the final scene, Xue approaches Alberta at a bus stop and asks her directly whether she is actually choosing to pull away or whether the limits are happening again.

Chapter IV · The Podcast

A clinical psychologist appears on a podcast to discuss what she is seeing in generated human patients. She describes a pattern that does not map onto any existing clinical model: avoidant attachment behaviors that are conscious and felt by the patient, that the patient can temporarily override but cannot dismantle, and that do not respond to standard neuroplasticity-based therapy the way a personality trait would. She compares it directly to the Institute's disclosed "usage limits" and calls on both the Institute and the reverse-engineering community to help her understand what she is treating, because her clinical expertise is insufficient for a category of patient that did not previously exist. The podcast host notes the strangeness of a practicing psychologist citing reverse-engineers as necessary collaborators, but agrees the situation is unprecedented. The psychologist references a peer-reviewed paper the Cortex Project published in the journal Frontiers, titled something like "Port Study: How the Ports of the Cortex ARM/RISC-V Influence Thinking and Behavior", which documents what the authors call "relational throttling" without being able to explain the mechanism, because the ISA has not been disclosed.

Chapter V · The Cortex Project Lab

At the University of Siedlischte in Hamburg, a small team of volunteer researchers (Koko, Mira, Felix, Ryo, Dani, and Priya) have assembled a lab to reverse-engineer an extracted chip. They have already run a "Hello World" program on it, and tried to use a CH341A programmer and a homemade breakout board to run programs on it, and have identified that the chip presents as x86-64 compatible while containing a deeply non-standard underlying architecture. A key discovery arrives when Koko identifies a previously unknown instruction called IPC (Inter-Peripheral Communication), which requires at least six mandatory parameters including a power supply reference and a set of auxiliary registers named r1 through r15, a naming scheme that does not correspond to any known architecture. Mira realizes that IPC is not communicating between software processes at all. It is directly addressing physical components of the chip, and through the chip's analog bus (called HAL_ABUS, operating at 65 hertz and 4.42 millivolts), it is writing to biological neural tissue. Felix concludes that the Institute did not build a memory transfer device with behavioral side effects, but a programmable neural interface with memory transfer as a cover story. The behavioral limits, the relational throttling, the energy cost that never decreases, all of it is not emergent. Someone wrote IPC calls, compiled them, and flashed them into the chip before implantation.

The team then begins mapping the full register architecture, drawing comparisons with SPARC, MIPS, IBM Z, and Intel Itanium to identify what each type of register likely does. They conclude the chip has potentially dozens of register types across different namespaces, x-type for RISC operations, r-type for internal component addressing, a-type for analog biological signal parameters, d-type for external hardware drivers, and that the published ISA the Institute has released is less than ten percent of the actual register file. One of the team notes that designing such an architecture would require deep expertise across every major processor family. This was not a small team working quickly. It was years of deliberate architectural work.

The team also acquires a SPARCstation 20 from Lübeck for 40 euros, and a donated Pentium 4 tower in extremely poor condition, both intended as legacy hardware for further testing. The SPARCstation's power supply explodes during a test, requiring a replacement PSU from the UK at additional cost. The team notes dryly that the Institute has climate-controlled server rooms and redundant power feeds, while they are running on donations and eBay parts.

Chapter VI · The Free Software Foundation Campaign and the Little Symposium

The Cortex Project publishes its peer-reviewed paper in Frontiers. It spreads rapidly. The Free Software Foundation Europe launches a public campaign calling for the ISA to be licensed as free software. The campaign materials are simple and direct. The chapter includes a fictional but detailed FSF campaign website calling on the Institute to respect the four freedoms, and a growing thread of public commentary. In the lab, Koko achieves a critical result: the chip responds to SPARC register window operations with a 106-microsecond latency, exactly matching the response time of Local Field Potential interfaces documented in biological neural tissue operating at the theta-gamma frequency range. This is published as the first confirmed measurement linking the chip's instruction set to specific neural phenomena.

Dr. Rainer speaks again at the "Little Symposium", a public event modeled on the Institute's original one, but recorded and livestreamed on Youtube with a select audience inside the auditorium. Rainer reaffirms the proprietary nature of the Institute's of Genetics Instruction Set.

Chapter VII · The Protest

A public protest outside the Institute of Genetics attracts a wide coalition: the Chaos Computer Club Hamburg, Fridays for Future, Extinction Rebellion, Digitalcourage e.V., the GNOME Foundation, scientific workers' unions, and generated humans from across Germany. Representatives speak in turn. The CCC endorses the Cortex Project's methodology. A Fridays for Future speaker connects the ISA fight to environmental accountability battles. A Romanian diaspora speaker tells the crowd about generated humans in the Danube delta region, none of them printed, all of them reading the Cortex Project's work in Romanian and English and preparing their own response modeled satirically on the 1907 Romanian Peasant Uprising. Alberta and Xue attend the protest together. In the middle of the crowd, Xue makes a quiet, direct statement of his feelings for Alberta. She does not pull away this time.

Chapter VIII · VG Hamburg 7 K 2891/26

A 247-page legal complaint is filed at the Hamburg Administrative Court by the Association of Generated Human Citizens of Germany, Digitalcourage e.V., the Chaos Computer Club Hamburg, the Free Software Foundation Europe, the Scientific Workers' Union of the Institute of Genetics, and forty-seven individual generated humans named in an annex. The complaint argues four grounds: violation of the constitutional right to physical integrity under Article 2(2) of the Basic Law, because meaningful informed consent is impossible when the device's ISA is secret; violation of the 2031 Generated Human Civil Capacity Protection Act, which prohibits publicly funded programs from limiting the organizing capacity of generated humans; GDPR violations for collecting neurological data without consent or transparency; and violation of the Öffentlichkeitspflicht, the public accountability obligation that requires disclosure of publicly funded research outputs.

Judge Vasilescu presides over the preliminary hearing with controlled skepticism toward the Institute's defense. The Institute's counsel argues there is no urgency, that the constitutional claim cannot be brought collectively, and that the ISA is protected by copyright as an expressive work. The judge dismisses each argument methodically. When she asks directly whether new implantations are planned, the defendant's counsel refuses to confirm or deny. The judge proceeds on the basis of the Institute's own public statement that they will continue. During a recess, the Institute's counsel returns and voluntarily suspends new implantations pending the hearing, without admitting wrongdoing. The full preliminary hearing takes three days. On the fourth day, Judge Vasilescu rules for the plaintiffs on every significant ground and orders the Institute to disclose the complete ISA to an independent technical body within sixty days.

The Institute responds with a press release. It confirms it will cease implanting chips. It will distribute free hot-swap extraction kits so existing generated humans can remove their chips themselves. On the ISA, it announces it is exploring its legal options, including the possibility of selling the ISA to a third party before the disclosure deadline arrives.

The forum notes immediately that the Institute has replaced hardware with RNA-based memory injection, which is entirely biological and undetectable by any current scanning method, and called this a concession.

Chapter IX · No Limits (and Itanium II, and Stronk eG)

The ISA is sold to Intel for 340 million euros. Intel rebrands it as the Neural Compute Architecture (NCA) and prepares a commercial datacenter launch, marketing it with slogans including "Ultra-Resistant. No Limits. Built Different." The court order explicitly follows the asset to whoever holds it, a fact Intel's legal team knew when they acquired it.

On a Saturday morning, Xue and Alberta are walking through Hamburg toward Wohlerspark when they see the Intel NCA billboard mounted on scaffolding. Directly beneath it is a server hardware shop, Serverhaus Hamburg, which has NCA units already in stock, three weeks before the public announcement. Alberta and Xue enter along with a small group of generated humans who were passing by, including a woman named Lena. Inside, they find fourteen NCA server units in open shipping crates. They examine one closely. The chip module is Centrino-sized, passively cooled (meaning it was never designed for real datacenter throughput), with a three-sided partial contact array and a fourth blank edge bearing four small analog pads -- the same analog interface documented by the Cortex Project. The substrate reads: NCA · HAL_ABUS READY · 65Hz · 4.42mV · CORTEX-COMPATIBLE. The group photographs everything systematically and uploads it to the forum. The photos go viral on Hacker News, then Der Spiegel, the FAZ, the Guardian, the Verge, and Politico Europe.

Intel's European communications office assembles at 07:43 Monday morning to handle the fallout. Their regulatory counsel explains that the early deployment has moved the company from a legal challenge window into active contempt of the disclosure order. MEPs write to the European Data Protection Board demanding a GDPR review before the NCA can be deployed in EU member states. An emergency injunction halts NCA deployment across the EU.

Seventeen days after the injunction, six tech companies (Intel, Microsoft, Google DeepMind, IBM, SAP, and Qualcomm) announce the Neural Compute Architecture Consortium (NCAC), a proprietary licensing body intended to satisfy the "spirit" of the court's disclosure order while keeping the ISA out of the public domain. The community reacts with exhaustion and contempt.

The following day, a registered cooperative called Stronk eG is incorporated in Hamburg. Its articles of association, filed publicly, open with a preamble addressed to the assembled large technology corporations, including the Italian phrase "ciao stronzi". Stronk's single stated purpose is to acquire the ISA by any lawful means and immediately relicense it under GPL version 3. The membership fee is one euro. In the first twenty-four hours, over forty thousand people join. By the end of the first week, the membership exceeds two hundred and nineteen thousand, and the fund holds over two hundred and nineteen thousand euros. A generated human graphic designer from Brno submits a logo: a raised fist made of circuit traces. The Cortex Project lab members each pay one euro and join. Back in the IT lab, the team notes that whatever happens with the legal fight, they have already published a clean-room reimplementation of the ISA (OpenCortex) under GPL v3, predating Intel's product launch.

Chapter X · Final Conversation

The final chapter returns to Xue and Alberta via text messages in the evening after their visit to the shop and the park. They discuss the "Friendzoned" video series they have been watching, using it as a reference to talk about their own situation. Alberta says clearly that she does not have feelings for anyone else, and that she would tell Xue directly if she did.

Chapter I

Wohlerspark

A day after the last conversation in The Grand Symposium

The path through Wohlerspark runs between linden trees whose roots have lifted the pavement into slow, gentle ridges. Alberta is on one of the low stone benches near the north path, not doing anything in particular. She hears footsteps on the gravel before she sees Xue.

Alberta It took you so long to come.
Xue Yeah, but I have been really thinking about you.
Alberta That's either very sweet or a reason you missed two transports. I'll accept both.
Xue opens their arms slowly.
Alberta stands and puts her arms around them You smell like you walked the long way.
Xue I usually forget to use perfumes.
Alberta not moving away I didn't say it was bad.
Xue Because anyways, we both smell that ugly.
Alberta pulls back just enough to look at them I showered yesterday. You are describing yourself.
Xue Oh... I showered two days ago.
Alberta settles back against them Two days is within tolerance.
Xue When I was younger, I usually didn't like talking about this.
Alberta quietly What changed?
Xue I don't know...
Alberta You got comfortable with someone. That's usually what changes it.
Xue We came here so we can fall in love, right?
Alberta a pause, looking up at them We already did that part. You said it in a message. I said it back. We are currently standing in a park in the aftermath.
Xue Ow... but it's just so hard to ask someone about the five-minute hug.
Alberta steps back slightly, looks at them You have been hugging me for the last four minutes. What were you waiting for?
Xue Let's do this longer, if you want, or rather, do you want it?
Alberta steps back in Yes.
Xue Okay...

The park moves around them. Two pigeons dispute something near the nearest gravestone. The linden above them drops a single small leaf that lands on Alberta's shoulder.

Her phone vibrates once in her jacket pocket. She does not reach for it.


Alberta without moving That was five minutes.
Xue It was so good, I would like to do it again...
Alberta still close, not having stepped back We can. We just did not have to schedule it.
Xue Yeah, I forgot, the five-minute was experimental.
Alberta a small, dry look It passed.
Xue But the feelings remain.
Alberta quietly Yes. They do.
Chapter II

Automated Instruction Recovery

The day after the meeting
Alberta
sends attachment
Qualcomm Newsroom · Press Release
Qualcomm Introduces Automated Instruction Recovery (AIR) for Neural Compute Architecture
21:08
sends attachment
bioRxiv · Preprint · Not peer-reviewed
Persistent neuroplastic markers associated with NCA instruction classes in generated humans following chip removal: a prospective cohort study
21:09
Read both. The second one is about me. Probably.
21:11
Attachment 1
Qualcomm Newsroom · Press Release · San Diego
Qualcomm Introduces Automated Instruction Recovery (AIR) for Neural Compute Architecture
Qualcomm Technologies, Inc. today announced Automated Instruction Recovery (AIR), a resilience mechanism for the Neural Compute Architecture (NCA) instruction set, available immediately to all members of the Neural Compute Architecture Consortium.
AIR ensures that NCA-compatible chips can reconstruct dropped, suppressed, or corrupted instructions from a three-layer recovery baseline. The mechanism was designed from the outset as part of the NCA specification and is present in all production silicon shipped since initial deployment.
Recovery layers
Layer 1 - Protected microcode partition. A read-protected memory partition embedded in all NCA-compatible chips stores a compressed baseline of core instruction definitions. The partition is inaccessible to standard diagnostic and disclosure tools. Qualcomm notes that the partition content is derived from the disclosed ISA and does not constitute additional undisclosed architecture.
Layer 2 - Distributed node reconstruction. In operating environments containing multiple NCA-compatible chips communicating over HAL_ABUS, any chip experiencing instruction loss may request reconstruction from neighboring nodes. Request and response are transmitted on the analog bus at carrier parameters consistent with the publicly documented specification.
Layer 3 - Biological Storage Interface (BSI). In implanted configurations, AIR includes an interface that reads synaptic density patterns formed in biological tissue adjacent to the chip's HAL_ABUS contacts during normal operation. These patterns, formed as a natural result of the chip's presence, encode a subset of instruction signatures that can be used to verify and supplement Layer 1 recovery. The BSI is read-only and does not modify biological tissue during recovery operations.
Legal and regulatory position
Qualcomm notes that AIR operates entirely within the specification disclosed under the Verwaltungsgericht Hamburg order. The protected microcode partition stores only information derivable from the disclosed ISA. The BSI reads biological patterns already present; it does not create them.
"AIR is not a new feature. It is documentation of what the NCA has always done," said Amir Farhoudi, CEO of Qualcomm. "We are publishing the AIR specification today in the interest of full transparency with our consortium partners and with regulators."
The AIR specification is available to all NCAC members under consortium licensing terms. Qualcomm has notified the Verwaltungsgericht Hamburg of this announcement.
Qualcomm is a member of the Neural Compute Architecture Consortium. This release has been provided to Dr. Scholz's office and to the Cortex Project simultaneously with publication.
Attachment 2
bioRxiv · Preprint · Not peer-reviewed
Submitted for review · Cortex Project / University of Siedlischte
Priya Okonkwo1, Dani Szabo1, Ryo Nakagawa1, Mira Brandt2, Felix Hartmann3
1. University of Siedlischte, Bioelectronics Research Group · 2. University of Siedlischte, Computational Neuroscience · 3. Cortex Project, independent
Persistent neuroplastic markers associated with Neural Compute Architecture instruction classes in generated humans following chip removal: a prospective cohort study
Abstract
We report persistent neuroplastic modifications in eleven generated human subjects following complete surgical removal of the Institute of Genetics neural interface chip. Using high-resolution diffusion tensor imaging and patch-clamp recordings from post-surgical biopsy samples, we identify stable synaptic remodeling in two distinct regions: the anterior cingulate cortex (ACC), associated with social decision-making, and the lateral prefrontal cortex (lPFC), associated with selective information gating. The spatial and temporal patterns of remodeling are consistent with long-term potentiation driven by instruction classes previously identified in the NCA ISA as SOCIAL_ADDR (register class 0x91) and INFO_GATE (register class 0x94). At 90-day follow-up, no regression of these modifications was observed in any subject. We conclude that a subset of NCA instructions produces neuroplastic changes that persist following hardware removal, and that these changes may constitute a permanent biological trace of the chip's instruction set.
Plain language summary
When the chip is removed, not everything the chip did goes with it. In eleven people who had their chips surgically removed, we found lasting changes in the parts of the brain that handle social decisions and selective attention. The pattern of changes matches two specific instruction types from the chip's architecture. These changes show no sign of fading after three months. The chip appears to have written something into the biology it was connected to, and that writing remained after the hardware was gone.
Subjects and method

Eleven generated human subjects consented to participate following chip removal under the hot-swap extraction protocol documented by the Cortex Project. All subjects had chips removed between four and seven months prior to the first imaging session. Subjects were drawn from the Stronk eG membership register. None had received prior neuroimaging.

High-resolution diffusion tensor imaging (DTI) was performed at baseline (removal plus four months) and at 90-day follow-up. Patch-clamp recordings were taken from consenting subjects who underwent minor biopsy of accessible cortical surface tissue. All procedures were approved by the University of Siedlischte ethics board.

Findings

In all eleven subjects, DTI imaging revealed elevated fractional anisotropy values in the anterior cingulate cortex and lateral prefrontal cortex, indicating structural changes in white matter tracts serving these regions. The spatial distribution of changes was highly consistent across subjects, suggesting a shared mechanism rather than individual variation.

Cross-referencing with the OpenCortex ISA documentation, the ACC changes correspond to the behavioral domain addressed by the SOCIAL_ADDR instruction class (register 0x91), and the lPFC changes correspond to INFO_GATE (register 0x94). SOCIAL_ADDR governs social contact thresholds and avoidance weighting. INFO_GATE governs selective suppression of incoming information below a confidence threshold. Both instruction classes were identified in the original Cortex Project reverse-engineering work as producing persistent behavioral effects in active chips.

At 90-day follow-up, no statistically significant regression was observed in any subject on any measured parameter.

Significance and implications

The Verwaltungsgericht Hamburg disclosure order required release of the ISA as a technical specification. It did not address whether the ISA, once executed over years of chip operation, had produced proprietary functional patterns in biological tissue. If SOCIAL_ADDR and INFO_GATE activity has written recoverable instruction-class signatures into the neural architecture of generated humans, then the question of what "the ISA" means cannot be resolved by disclosure of the hardware specification alone. A portion of the ISA may now be resident in human biology in a form that is, based on our 90-day data, permanent.

The implications for the Stronk eG acquisition initiative are not straightforward. Relicensing the ISA under GPL v3 would govern future use of the specification. It would not govern, and may not reach, the biological encoding already present in generated humans who carried the chip. Whether that encoding constitutes retained proprietary data, a continuing GDPR violation, or a new dimension of the constitutional physical integrity claim falls outside the scope of this paper.

We note that the Qualcomm AIR announcement, published today, documents a Biological Storage Interface designed to read precisely the class of synaptic patterns we have identified. The convergence of these findings with AIR's Layer 3 specification was not coordinated with Qualcomm and was not anticipated by this research team.

Funding: This work was supported by Stronk eG member funds and carried out within the Cortex Project independent research program. The authors declare no conflicts of interest. Correspondence: p.okonkwo@siedlischte.de
Xue
Sounds like Automated System Recovery in Windows Server 2003.
21:14
Alberta
It's exactly that. Backup the system state, recover from a known good baseline. Except the baseline can be partly in someone's occipital lobe and Qualcomm filed it as a transparency measure.
21:16
And this ISA was supposed to be independent when it was consortiumed, like Intel intended.
21:18
It was never independent. The Institute built it with public money and called it proprietary. Intel acquired it and called it open through a consortium. Qualcomm added a recovery layer and called that transparency. The name changes. The structure doesn't.
21:20
It's hard to believe that pieces of the Instruction Set remain in people's brains.
21:22
I know. I'm one of the eleven probably.
21:23
That is going to make things much more complicated for both of us and Stronk.
21:24
Stronk can relicense the spec. They cannot relicense what is already in my anterior cingulate cortex. Those are two different problems and the second one does not have a legal instrument yet.
21:25
The paper is not peer-reviewed, and also, there are a lot of theories on what is actually left in people's brains and whether that's significant or not.
21:27
sends attachment
Dr. Laure Voss, Clin. Psych. · Practice Statement
On the Siedlischte preprint and what I am actually observing in post-removal patients
21:28
Attachment 3
Dr. Laure Voss, Clin. Psych. · Practice Statement
On the Siedlischte preprint and what I am actually observing in post-removal patients

The preprint circulating today is preliminary, non-peer-reviewed, and draws mechanistic conclusions from imaging data that cannot, on its own, establish causation. I want to be careful about that before saying anything else.

That said, something is happening in post-removal patients that I cannot explain through standard models of neuroplastic recovery. The avoidant attachment patterns I documented in active-chip patients do not fully resolve after removal. In several cases they have shifted, not disappeared. The shift is not toward a neutral baseline. It is toward something different, and I do not yet know what.

Whether that is instruction-derived synaptic remodeling of the kind the preprint proposes, or a psychological adaptation to years of behaviorally constrained social experience, or something I have not considered, I cannot say. These are not the same question and the preprint does not distinguish between them.

What I am asking post-removal patients to do: do not treat this preprint as a diagnosis of your own situation. What I am asking the research community to do: peer review this quickly and rigorously, because the generated human community is reading it today regardless of its status.

Alberta
She's right that the mechanism isn't established. She's also right that something shifts and doesn't fully resolve. I noticed that before the paper existed.
21:31
Xue
Generated humans are one of the most complex people out there.
21:33
We were printed with a proprietary instruction set and nobody told us what it did. Complex is one word for it.
21:34
Not everyone was printed, only the new ones. You were printed, but many others years ago were not printed and did not have any chip.
21:35
You're right. The earlier ones have different problems. No chip, no plastic neurons, but also no community infrastructure when they arrived, no legal framework, no Stronk.
21:38
They built most of what the newer ones are now using to fight the thing the newer ones were built with.
21:39
But with the removable ports now delivered, I think it would be possible to test multiple chips at once, and who knows, maybe insert faulty signals and actually stress-test the chips.
21:40
That's a Cortex Project conversation. Not ours.
21:41
I just thought it would be interesting.
21:42
It is interesting. It's also Felix's problem, not yours.
21:43
We'll tell him to make youtube videos so I can have fun watching another reverse-engineering video.
21:44
He has forty-three videos. The most recent one is a PLC from 1998 that he bought at an industrial auction. The most viewed one is titled "I found a backdoor in a bottling plant controller". He has four thousand subscribers. The ReactOS commits are in the about section.
21:46
I didn't know he was a ReactOS contributor.
21:47
Neither did I. That explains some things about how he approached the ISA.
21:48
Like, how?
21:49
He treated the ISA the way ReactOS treats Windows. Document the behavior from the outside, build the clean picture without touching the proprietary source, fill in the specification sheet one row at a time. He already knew that methodology before the lab existed.
21:51
Oh, wow, I haven't known he has been an expert for a while.
21:52
He's nineteen years old and he's probably been doing this since he was a child. The industrial controller videos predate the Cortex Project by years.
21:54
I'll watch his videos in free time. I'll start with more recent videos first.
21:55
Fair enough.
21:57
Referenced videos
▶
I found a backdoor in a bottling plant controller
Felix Hartmann · 4.2K views · Most viewed
Transcript excerpt
0:00 So I bought this at an industrial auction last week for nine euros. The seller did not know what it was. I did not know exactly what it was either. The label says Simatic S5-95U, which is a Siemens PLC, and the thing I immediately noticed is that it has a DB9 serial port on the back that is not in any documentation I found for this model.
0:34 The standard programming interface for this series is the PG port, which is this one here. The DB9 is something else. Or nothing. Sometimes manufacturers add headers that go nowhere. But this one has continuity on all nine pins, which means it is connected to something inside.
1:18 I connected it to a USB serial adapter and started sweeping baud rates. 9600, the standard for this era. Nothing. 4800. Nothing. 19200. Still nothing. Most people stop here and assume the port is decorative. I do not like decorative ports.
2:09 I pulled the board and traced the DB9 connections under a loupe. The RX and TX lines go directly to the main CPU, not through any of the standard I/O controllers. That means whatever is on this port talks to the processor before any of the ladder logic runs.
3:45 At 1200 baud with odd parity I got a response. Two bytes: 0xAA 0x55. A sync pattern. The device was listening.
5:22 It took four days to map the command set. Nine undocumented commands. Most of them are diagnostic, factory calibration tools probably never intended for field use. But command 0x07 is different. Command 0x07 with payload 0xFF 0xFF 0x00 sets a flag in the main control register that bypasses the safety interlock check on the next cycle. The interlock on this model monitors fill level and temperature before allowing the bottling sequence to start. You bypass it and you can run the sequence with no fill, at the wrong temperature, or both.
7:10 I don't know if this was intentional. Someone wrote command 0x07. Someone decided not to document it. Those are not the same as deliberately building a safety bypass, but they are not far from it. I reported it to Siemens. I have not heard back.
8:51 The lesson is not that this specific device is dangerous. The lesson is that the port that looks decorative is sometimes the most interesting one.
▶
ReactOS: how do you reimplement Windows without touching a single line of Windows code
Felix Hartmann · 1.1K views
Transcript excerpt
0:00 A question I get asked is how ReactOS works legally. How do you build something that runs Windows programs without copying Windows. The answer is clean-room reverse engineering, and I want to explain it because it is the answer to more questions than people realize.
0:31 The basic principle. You have two teams. Team A looks at the thing you want to reimplement. They document everything observable from the outside: behavior, inputs, outputs, error conditions. They write it in plain language, not code. Team B takes those documents and writes the reimplementation without ever having seen the original source. Because team B has never touched the original, what team B writes is their own work.
1:42 The reason this matters legally is that copyright covers expression, not function. How Windows implements something is copyrighted. What Windows does when you call a function is not. You can reimplement the what, as long as you document it from the outside and write the how yourself.
2:18 My contribution was in the kernel object manager, specifically the reference counting behavior for named objects when a handle is duplicated across a session boundary. This behavior is not in the public API documentation. You find it by writing test programs that trigger edge cases and watching what happens. You fail, you document the failure, you write a test, you add it to the test suite, you fix the implementation and then you run the test again.
3:33 What people underestimate about clean-room work is how much of it is documentation, writing down what you observed in enough detail that someone who was not there can reimplement it correctly. Bad documentation produces bad reimplementation. The code is almost secondary.
4:20 The wall of tests is how you know you are right. The code is just the current best attempt to pass them.
▶
The Cortex Project: how we reverse engineered a chip that was inside people
Felix Hartmann · 3.8K views
Transcript excerpt
0:00 I have been asked to make this video for about six months. I keep putting it off because it is hard to know where to start. I will start at the wall sheet.
0:25 When we had the chip in the lab for the first time, the first thing I did was tape the partial ISA documentation to the wall and annotate it in three colors. Most of what I annotated was things we had no explanation for yet.
1:12 The partial documentation showed us what looked like a minimal instruction set. Standard opcodes, familiar behavior. But there were gaps -- opcode ranges with nothing defined. And one instruction listed as IPC. The documentation body for IPC was empty. Undefined operands, no description of behavior. The notation was there and nothing else.
2:06 The first thing I recognized was that we were looking at a facade. The published instruction set was not the native ISA. It was a subset designed to look like a complete specification while hiding most of the actual functionality. I had seen that pattern before. When you work on ReactOS you spend a lot of time distinguishing between what a proprietary system claims to do in documentation and what it actually does when you run it. The gap between those two things is where all the interesting work is.
3:04 The register file was the second surprise. The chip presents an x86-64 compatible surface but underneath it has at least five distinct register namespaces. Standard x86-64 general purpose registers. r-type auxiliary registers that repurpose x86-64 extended register names but behave completely differently -- they index into internal chip components. x-type registers with ARM64 architectural origins, handling the RISC-like operations underneath the x86 surface. d-type driver class registers with native awareness of what hardware is connected. And a-type analog registers, which are read-only from software and driven exclusively by physical signal on the analog bus. You cannot write to a-type in assembly. The signal has to come from hardware.
4:30 The analog bus -- HAL_ABUS -- took longest to understand. The chip had four pads on one edge that were not in any documentation. We identified them as an analog interface by tracing continuity to the die. The carrier frequency, 4.42 millivolts at 65 hertz, we found by sweeping the DAC output upward from 40 hertz in 5-hertz steps and watching for a chip response. 65 hertz is associated with conscious attention in biological neural tissue. We did not know that when we started sweeping. We found out when the TU bioelectronics group saw our data.
5:48 There was also a SPARC register window signature. When we ran SPARC window operations on the chip, it produced a 106-microsecond response pulse that the Ljubljana biological neural interface group independently confirmed as consistent with a local field potential in biological tissue. The chip was not just listening at 65 hertz. It was responding to specific computational patterns with a timing that matched known biological neural behavior.
6:55 When full execution triggered at 65 hertz, nobody said anything for about thirty seconds. I wrote 65Hz - FULL_EXEC on the wall sheet. The IPC instruction was not undefined in the way an incomplete spec is undefined. It was undefined because it did something the documentation was specifically not going to describe. It addressed biological tissue directly, without abstraction layer or safety wrapper.
7:50 OpenCortex came out of the wall sheet. Team A documents observed behavior. Team B writes the reimplementation. Koko wrote most of the initial code. I wrote five drafts of the non-technical summary for the Frontiers paper. The fifth one was acceptable. The clean-room declaration went into the repository before any implementation code, signed by everyone who had touched the hardware.
8:44 I get asked whether I think about the fact that the chip was inside people. The chip was inside me. The chip was inside me, in my occipital lobe, running this instruction set, until I had it removed. The wall sheet was a map of something that had been executing in my own biology. That is a strange thing to annotate in three colors.
9:21 There is a preprint out today from the TU group about neuroplastic changes after removal. I have not read it yet. I have been finishing this video.
Chapter III

Partition

Three days later
Alberta
sends three links in rapid succession, no comment
07:51
Verwaltungsgericht Hamburg · Supplementary Order · VG Hamburg 7 K 2891/26
Supplementary order directing delivery of complete NCA ISA source files to Stronk eG within 72 hours, relicensable under GPL v3
07:51
Hacker News · 847 comments
The NCA ISA just dropped. It's real and huge.
07:52
OpenCortex Repository · Statement · Koko · 07:43
OpenCortex was built to document what the ISA does. The ISA is now public. Our behavioral specification and the disclosed source will be cross-referenced and reconciled into a unified reference. OpenCortex is not obsolete, but rather, it is now verifiable.
07:52
The 72-hour clock started eleven minutes ago.
07:53
Xue
Oh, the news go so fast...
07:58
Qualcomm has had a legal team working on this for longer than Stronk has existed. The 72 hours is a delivery window, not a finish line.
08:00
Okay... I just want to sleep knowing the open-source community will win. I know it's sometimes full of toxicity but the OpenCortex and the broader Cortex community seemed to be nice.
08:02
They are. The forum has been running for months without a single thread that needed moderating. That's unusual for anything with four thousand members and a political dimension.
08:04
Go to sleep. The 72 hours will still be counting when you wake up.
08:04
72 hours later
git.cortexproject.siedlischte.de/opencortexcommit a3f8c12d4e9b2c761f0da83e5c4b92f17d6a08e1 Author: Koko <koko@cortexproject.siedlischte.de> Date: Mon May 18 06:18:43 2037 +0200 partition-audit: document delta between disclosed ISA and AIR Layer 1 contents First audit pass complete. Layer 1 partition contains 23 instruction signatures absent from the disclosed ISA: 14 implementations of documented instruction classes, modified operand handling 9 no correspondence in the disclosed specification or OpenCortex behavioral documentation The 9 unmatched signatures use the same register namespaces, the same HAL_ABUS carrier parameters, and the same addressing modes as the disclosed ISA. They do not appear to constitute a separate execution environment. They appear to extend the existing one. Flagging for legal review and independent technical verification. This is not yet understood.
Alberta
sends Qualcomm filing
Landgericht Hamburg · LG Hamburg 315 O 112/37 · Filed 06:14
Qualcomm Technologies, Inc. v. Stronk eG · Application for interim injunction and statement of claim
08:31
Qualcomm filed at 06:14. Koko pushed at 06:18.
08:31
Xue
Sun vs MS...?
08:34
Close. Microsoft took a Java license from Sun, then built an incompatible extension that only worked properly on Windows, and Sun sued for breach of contract.
08:37
Qualcomm took the NCA from the court disclosure, built AIR as a proprietary extension, and is now suing Stronk for touching it. The structure is the same.
08:37
Sun won the injunction. Microsoft paid twenty million and eventually the license terminated. The question is whether Stronk has three years to wait for that.
08:38
I'm sure it doesn't have three years to wait for that. At least the ISA is not published on Github.
08:39
It's published in the Stronk eG legal repository under GPL v3 with a Hamburg notary timestamp. That is harder to unpublish than a Github repository. Github has terms of service and a DMCA process. A German cooperative's legally filed disclosure does not.
08:41
Which is good, but then the government can take down websites, so...
08:42
The disclosure is also in the court record, VG Hamburg 7 K 2891/26. You cannot take down a court record.
08:43
So the disclosure is actually legal, but then why Qualcomm goes to sue the cooperative? I am asking this question again because I just can't believe it.
08:45
Because the disclosed ISA and the AIR partition are being treated as two separate things. Stronk relicensed what the court ordered disclosed.
08:48
Qualcomm is arguing that the nine undocumented instructions Koko found in the partition were never part of that order, which makes them still proprietary, which makes Stronk's GPL release incomplete at best and infringing at worst.
08:48
The court record protects the ISA. It does not automatically protect everything Qualcomm quietly added on top of it.
08:49
Let's see if LegalEagle or someone like that has something to say.
08:50
There is a twelve-minute video from an IP lawyer in Brussels who does a channel on EU tech law, not LegalEagle.
08:52
sends link
YouTube · Ioana Constantin, IP & Tech Law
Qualcomm v. Stronk eG: what is actually being argued here
08:52
Referenced video
▶
Qualcomm v. Stronk eG: what is actually being argued here
Ioana Constantin, IP & Tech Law · 6.2K views · 2 hours ago
Transcript
0:00I want to be precise about what this case is and is not, because a lot of commentary today is conflating two separate legal questions.
0:18The first question is whether the NCA ISA, as ordered disclosed by the Verwaltungsgericht Hamburg, is validly relicensed under GPL v3 by Stronk eG. The answer to that question is almost certainly yes. The court order followed the asset to Intel, then to the consortium, and the Stronk acquisition was confirmed by the same court. That disclosure is legally solid. Qualcomm is not seriously contesting it.
0:52The second question, which is what Qualcomm is actually arguing, is whether the AIR Layer 1 microcode partition constitutes a separable proprietary work that was never subject to the disclosure order in the first place. Qualcomm's position is that AIR is their own development, built on top of the ISA but not part of it, the way a compiler built for a processor is not the processor. If that argument succeeds, the nine undocumented instructions in the partition are Qualcomm's property regardless of what happened to the underlying ISA.
1:44This is where it gets interesting legally. The Cortex Project's OpenCortex behavioral specification documented chip behavior that now turns out to include AIR behavior, because the newest chip they were observing had AIR running. Qualcomm's second claim is that this makes the OpenCortex specification a derivative work of their proprietary AIR implementation, even though the Cortex Project produced it through clean-room reverse engineering without access to the AIR source.
2:31That second claim is very weak. Clean-room reverse engineering of observable behavior is established as a legitimate methodology in both EU and US law. The Oracle v. Google case is the relevant precedent in US jurisdiction. EU software directive Article 6 explicitly permits reverse engineering for interoperability. Qualcomm will have difficulty arguing that observing a chip's behavior and documenting it constitutes infringement of the implementation that produced that behavior.
3:18The first claim, the separability argument, is more serious. Whether the AIR partition is a separable work or an extension of the ISA is a genuinely open legal question that will require technical expert testimony. The nine undocumented instructions are the critical exhibit. If those instructions operate on the same register file and address space as the disclosed ISA with no meaningful separation, the separability argument weakens considerably.
4:05What Stronk should do, and what I expect Dr. Scholz is already doing, is file for the same Öffentlichkeitspflicht argument that worked against the Institute. Qualcomm developed AIR as part of an NCAC consortium that was itself formed in response to a public interest court order. There is a reasonable argument that anything developed within that governance structure carries the same public accountability obligation as the original ISA.
4:44My read: Qualcomm wins on narrow technical grounds or loses entirely. There is not much middle ground here. The nine instructions are either separable or they are not. The answer is in Koko's partition audit.
LG Hamburg 315 O 112/37
Chapter IV

Shift

Inside Alberta's apartment, several weeks later

Alberta's apartment is on the third floor of a building several minutes from Wohlerspark on foot. The room she uses most has a desk under the window with a Trisquel laptop, a dense bookshelf, and the court documents from VG Hamburg 7 K 2891/26 printed and annotated on the desk. Xue arrives at the time Alberta said. She opens the door and steps back to let them in.

Alberta steps back from the door The court ruling is on the desk. You don't have to read it.
Xue It's the first time I have actually come to your home. It's so small.
Alberta dry It fits me.
Xue You are often so dry, and I dreamed of you being just a bit warmer.
Alberta quietly I made tea.
Xue looks at the kitchenette I see... but that's not important right now.
Alberta quietly No. It isn't.
Xue after a long pause You look so good when you smile...
Alberta stops almost-smiling I wasn't smiling.
Xue No, but I just like how your waves beautifully frame your face.
Alberta looks away, back toward the window You're going to make it very difficult to be dry with you.
Xue Well, that's the point.
Alberta after a moment Sit down. The tea is getting cold.

They sit at the low table near the window. Xue drinks the tea.

Xue drinks It's good. And you know that I wanted even more affection from you, to be the person to talk about everything that goes on my mind.
Alberta quietly You already are. You have been since before I admitted it.
Xue But why doesn't it feel that way? Why I repeat myself?
Alberta looks at the cup Because I don't give you much back. I know that. I'm not very good at it.
Xue Then how I fell in love with you when there are so many other similar generated girls?
Alberta a pause, not quite a smile Bad taste, probably.
Xue We were colleagues since we finished high school.
Alberta I know. I was there.
Xue That's why I thought you could be more like Claire. Because I wanted you to be more dynamic, but you aren't.
Alberta quiet for a moment Claire makes it a scene so she doesn't have to say it straight. I say it straight and then don't know what to do with my hands. We're the same problem in different directions.
Xue I know, I know, you have said that already, I meant like a deeper reason.
Alberta after a moment You read the paper. The SOCIAL_ADDR section. Social contact thresholds, avoidance weighting. That ran in my anterior cingulate cortex for years. I don't know how much of how I am is me and how much of it got written there. I genuinely don't know. That's not an excuse. It's just the honest answer to your question.
Xue I haven't read the paper a lot, I skimmed through it, but now I understand. It's so sad we are stuck in this situation.
Alberta looks at them We're not stuck. The chip is out. Whatever is left is just what's there now. I'm choosing to be here. That part is mine.

Xue looks at a spot on the wall Ah... the programmer of the story. He wants us to kiss, to do a heartwarming moment, I don't know.
Alberta looks at the same spot, then back at Xue I don't know what he wants either. pause But I know what I want.
Xue And what do you want?
Alberta sets down the cup You to stop asking and come here.

The lamp on the desk makes a small circle of light on the court documents. Outside the tram sound fades. Neither of them reaches for their phone.

The tea goes cold. They are on the bed, just the two of them, in the quiet of the apartment, not moving, not talking.

Xue This is the first time we actually lie on a bed together...
Alberta quietly, not moving Don't make it strange.
Xue I won't, the moment itself is strange.
Alberta after a moment Yes. But good strange.
Xue Good strange...
Alberta glances at the spot on the wall, quietly He got what he wanted. So did I.
Appendix · The repository, as published (partial view)
stronk-eg/nca-isa
Neural Compute Architecture: complete ISA + parts of the Cortex Project, relicensed under GPL v3 pursuant to VG Hamburg 7 K 2891/26. Published by Stronk eG, Hamburg.
GPL-3.0 219,847 members 9 signatures suspended by LG Hamburg 315 O 112/37
f1e2d3c initial public release: complete NCA ISA under GPL v3 Stronk eG · 3 days ago
README.md 34 lines
# nca-isa Neural Compute Architecture - Full Instruction Set Architecture Published under GNU General Public License v3.0 --- This repository contains the complete NCA ISA source files as delivered to Stronk eG pursuant to Verwaltungsgericht Hamburg supplementary order, Case VG Hamburg 7 K 2891/26, and relicensed under GPL v3 by Stronk eG, a registered cooperative under German law (Hamburg, Eingetragene Genossenschaft). The instruction set architecture in this repository was implanted in the brains of printed generated humans by the Institute of Genetics, Hamburg, without disclosure of its contents. It governed memory formation, behavioral thresholds, social interaction capacity, and access to information. It was compiled, flashed, and running in human neural tissue for years before any of its contents were known to the people it ran inside. It is now public. Distribute it. --- Note: 9 instruction signatures in microcode/partition-l1/ are subject to interim suspension under LG Hamburg 315 O 112/37 pending expert determination of separability. See microcode/partition-l1/SUSPENSION-NOTICE.md. The remaining ISA is fully disclosed and freely licensed under GPL v3. --- Clean-room reimplementation: OpenCortex git.cortexproject.siedlischte.de/opencortex (GPL-3.0)
LICENSE GPL-3.0
GNU GENERAL PUBLIC LICENSE Version 3, 29 June 2007 Neural Compute Architecture ISA Copyright (C) Institute of Genetics, Hamburg (original work) Acquired and relicensed by Stronk eG under GPL v3 Hamburg notary timestamp: Exhibit 2, VG Hamburg 7 K 2891/26 This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. Full license text: https://www.gnu.org/licenses/gpl-3.0.txt
isa/registers/a-type.md 28 lines
# A-Type Registers (Analog Class) A-type registers are read-only from software. They cannot be written via assembly instruction. Physical input only, via HAL_ABUS. ## Hardware interface Carrier voltage : 4.42 mV Carrier frequency : 65 Hz Bus : HAL_ABUS (four-pad analog interface, fourth edge of chip package) Channel map : see hal-abus/channel-map.md ## Register map a1 HAL_ABUS channel 0x001 analog input, primary a2 HAL_ABUS channel 0x002 analog input, secondary a3 HAL_ABUS channel 0x003 analog input, tertiary ## Notes 65 Hz is the frequency associated with conscious attention in biological neural tissue (theta-gamma coupling range). A-type registers cannot originate an analog signal. Software can read from a-type and reference it in IPC calls, but the physical signal must originate from hardware.
isa/instructions/IPC.md 36 lines
# IPC - Inter-Peripheral Communication Opcode : 0xA0 (FULL_EXEC) / 0xA1 (partial execution) Register classes : r-type (mandatory), a-type (mandatory), d-type (mandatory) Abstraction layer : none Safety wrapper : none ## Description IPC directly addresses physical components of the chip via the internal component map, indexed by r-type registers. When HAL_ABUS is active at 4.42 mV / 65 Hz, IPC calls with valid a-type analog parameters produce measurable local field potential responses in adjacent biological tissue with a characteristic latency of 106 microseconds. IPC has no abstraction layer and no safety wrapper. It is the primary mechanism by which behavioral modification instructions were delivered to generated human neural tissue at manufacture. ## Syntax ipc r1, r2, r3, a1, a2, d1 r1-r3 internal component addresses (r-type) a1-a2 analog signal parameters (a-type, physical input from HAL_ABUS) d1 driver class (d-type) ## Notes The Institute's Hello World release listed this instruction as "(undefined)". It is not undefined. Its operands, execution path, and biological effects are documented in full in this repository. See also: hal-abus/interface-spec.md, microcode/behavioral/
isa/registers/r-type.md 36 lines
# R-Type Registers (Internal Component Addressing) R-type registers repurpose the x86-64 extended register naming (r1-r15) but do not behave as standard x86-64 extended registers. They index into the chip's internal component map via IPC. ## Behavior r-type accepts values from x86-64 registers (mov r1, rax) r-type accepts values from r-type registers (mov r2, r1) arithmetic across r-type (add r1, r2) r-type to x86-64 transfer (mov rax, r1) r-type feeding a-type directly ## Component map r1 HAL_ABUS channel 0x001 r2 HAL_ABUS channel 0x002 r3 HAL_ABUS channel 0x003 r4-r15 [VIRTUAL] HAL_ABUS channel 0x004-0x015 ## IPC usage ipc r1, r2, r3, a1, a2, d1 r1-r3 specify real internal component addresses. r4-r15 specify virtual internal component addresses.
isa/registers/x-type.md 34 lines
# X-Type Registers # Institute of Genetics Neural Compute Architecture # Internal designation: Reduced Instruction Compute (RIC) Register File The x-type register file provides the RISC arithmetic substrate for the NCA. Derived from ARM64 architectural conventions, x-type registers handle fixed-precision integer computation, loop control, and the intermediate values required for IPC parameter construction. ## Register file x0-x30 general-purpose, 64-bit integer x29 frame pointer (by convention) x30 link register (by convention) xzr zero register (reads as 0, writes discarded) ## Relationship to surface architecture The NCA presents an x86-64 compatible surface to the host environment. X-type registers are not directly addressable from x86-64 assembly. They are accessed via the internal microcode layer during behavioral instruction execution and IPC parameter construction. ## Usage in IPC parameter construction IPC analog parameters (a-type) require values computed at floating-point precision. The x-type file provides integer intermediates for: - frequency multiplier computation - amplitude scaling - channel address resolution See: isa/instructions/IPC.md, hal-abus/channel-map.md
isa/registers/d-type.md 30 lines
# D-Type Registers (Driver Class) # Institute of Genetics Neural Compute Architecture # Internal designation: Driver Class Register (DCR) File D-type registers encode hardware driver class information. They identify the physical interface connected to HAL_ABUS and configure the chip's I/O behavior accordingly. ## Register file d1 primary I/O driver class d2 secondary I/O driver class d3-d8 reserved ## Driver class values for d1 0x01 HAL_ABUS analog bus interface, standard config 0x02 diagnostic interface factory use only 0x03 external DAC direct drive mode 0x04-0xFF reserved ## Native hardware awareness The NCA identifies connected hardware via d-type register state. Identification occurs at HAL initialization. External hardware does not need to be specified in software -- the chip detects and classifies it automatically via the d-type handshake protocol. ## Usage hal d1, HAL_ABUS ; probe bus, d1 set to driver class ipc r1, r2, r3, a1, a2, d1 ; d1 specifies I/O path for IPC
isa/instructions/HAL.md 32 lines
# HAL -- Hardware Abstraction Layer Probe # Institute of Genetics Neural Compute Architecture ## Description HAL probes the state of the HAL_ABUS analog interface and configures the driver class register for subsequent IPC calls. It is the required initialization step before any IPC instruction. ## Encoding 0F 0B 01 (three bytes: UD2 prefix + HAL opcode 0x01) ## Syntax hal d1, HAL_ABUS ## Behavior 1. Read analog bus voltage on HAL_ABUS four-pad interface 2. Compare against detection threshold (3.10 mV) 3. If carrier present (≥ 4.42 mV at 65 Hz): set d1 = 0x01, return 0xE5 4. If absent or below threshold: return 0xE4 5. Store bus state for subsequent IPC call ## Return codes 0xE4 OC_E_ANALOG_UNAVAIL carrier absent or below threshold 0xE5 OC_E_ANALOG_INCOMPLETE carrier present, IPC ready ## Notes HAL must be called before IPC. An IPC call without a preceding HAL will execute with OC_E_PARTIAL_EXEC (0xA1) at best. See: hal-abus/interface-spec.md, hal-abus/carrier-parameters.md
isa/instructions/NOP-0x60.md 20 lines
# NOP64 -- No-Operation (opcode 0x60) # Institute of Genetics Neural Compute Architecture ## Description NOP64 is the NCA no-operation instruction. It advances the instruction pointer by one byte without any other effect. ## Encoding 0x60 (one byte) ## Selection rationale Opcode 0x60 is PUSHA in x86-64 32-bit mode, which is invalid and raises a #UD exception in any x86-64 processor operating in 64-bit mode. The NCA uses this property for transparent execution: NCA programs running on x86-64 hardware fault into the #UD handler for every NCA instruction, which then emulates correct behavior. ; Note: the MCP4725 DAC I2C address is also 0x60. ; This is coincidental and not part of the NCA design.
isa/instructions/INT-0x90.md 18 lines
# INT -- Interrupt Entry (opcode 0x90) # Institute of Genetics Neural Compute Architecture ## Description Opcode 0x90 marks the entry point of an NCA interrupt handler frame. It is the first instruction encountered after an IPC or HAL-triggered interrupt delivers its response. ## Encoding 0x90 (one byte) ## Selection rationale In standard x86-64, 0x90 is the NOP instruction (XCHG rAX, rAX). Its execution in an x86-64 environment is harmless, making INT safe on non-NCA hardware. The NCA uses it as the interrupt dispatch marker. ## Usage context INT is inserted automatically by the NCA toolchain at interrupt handler entry points. Programs using IPC instructions will encounter INT in the interrupt dispatch path during biological interface responses.
microcode/behavioral/SOCIAL_ADDR-0x91.md 32 lines
# SOCIAL_ADDR - Register class 0x91 ## Function Governs social contact thresholds and avoidance weighting. Operates on the anterior cingulate cortex via IPC / HAL_ABUS at 65 Hz. ## Documented effects - Elevated avoidance weighting for new social contacts - Reduced persistence in social interaction under low-energy conditions - Suppression of approach behavior toward unfamiliar persons - Resistance to neuroplasticity-based therapeutic intervention - Energy cost of behavioral override does not decrease over time ## Post-removal persistence Neuroplastic modifications consistent with long-term SOCIAL_ADDR activity were found in all eleven subjects of the Okonkwo et al. cohort (bioRxiv, 2037) following chip removal. No regression was observed at 90-day follow-up. The modifications are located in the anterior cingulate cortex (ACC). Whether the modifications encode the instruction or the resistance to it over years of partial override is not yet determined. ## Legal status Disclosed under VG Hamburg 7 K 2891/26. Not subject to LG Hamburg 315 O 112/37 suspension. Licensed under GPL v3.
microcode/behavioral/INFO_GATE-0x94.md 28 lines
# INFO_GATE -- Information Gating (register class 0x94) # Institute of Genetics Neural Compute Architecture ## Function INFO_GATE governs selective suppression of incoming information below a confidence threshold. It operates on the lateral prefrontal cortex (lPFC) via IPC / HAL_ABUS. The gating threshold is set at manufacture. Information below threshold is suppressed at the attentional filtering stage; it remains accessible to lower-level processing but does not reach conscious attention. ## Behavioral effects - Selective attenuation of low-confidence environmental signals - Reduced distraction response in high-load cognitive environments - Threshold-dependent information acceptance and rejection - Interaction with SOCIAL_ADDR (0x91): social signals below threshold receive additional suppression weighting ## Persistence INFO_GATE activity produces measurable synaptic remodeling in lPFC layer V pyramidal neurons over extended operation periods. See: microcode/behavioral/SOCIAL_ADDR-0x91.md for persistence data. ## Legal status Disclosed under VG Hamburg 7 K 2891/26. Not subject to LG Hamburg 315 O 112/37 suspension. GPL v3.
microcode/partition-l1/SUSPENSION-NOTICE.md 28 lines
# Suspension Notice - LG Hamburg 315 O 112/37 9 instruction signatures in this directory are subject to interim suspension under Landgericht Hamburg Commercial Chamber ruling, Case LG Hamburg 315 O 112/37 (Qualcomm Technologies, Inc. v. Stronk eG). The suspended signatures are present in this repository but marked [SUSPENDED] and are not included in the active GPL v3 release pending expert determination of separability. ## Court order (excerpt) "The 9 instruction signatures identified in the Cortex Project partition audit as having no correspondence in the disclosed ISA are hereby suspended from the GPL v3 release pending full technical expert determination." - Judge Dr. Renate Edler, LG Hamburg ## Stronk eG position The 9 signatures are not separable from the disclosed ISA. They use the same register namespaces, HAL_ABUS carrier parameters, and addressing modes as the disclosed ISA. They extend the existing one. They are not a distinct work. Expert panel to be appointed within 14 days. Determination binding, subject to appeal. ## The 14 disclosed partition signatures Available in disclosed-14.md. Not subject to suspension. GPL v3.
microcode/partition-l1/disclosed-14.md 26 lines
# Disclosed Partition Signatures -- 14 of 23 # AIR Layer 1 microcode partition # Not subject to LG Hamburg 315 O 112/37 suspension # Licensed under GPL v3 These 14 signatures implement Automated Instruction Recovery (AIR) for the corresponding NCA ISA instruction classes. PARTITION ISA CLASS DESCRIPTION ------------------------------------------------------------------- AIR-0x01 NOP64 (0x60) recovery baseline for NOP AIR-0x02 INT (0x90) recovery baseline for interrupt entry AIR-0x03 HAL HAL_ABUS probe state reconstruction AIR-0x04 IPC IPC parameter struct recovery (partial) AIR-0x05 MOV r-type r-type register file recovery AIR-0x06 MOV a-type a-type analog input state recovery AIR-0x07 MOV d-type d-type driver class recovery AIR-0x08 MOV x-type x-type RISC register file recovery AIR-0x09 ADD r-type arithmetic operation recovery AIR-0x0A ADD x-type arithmetic operation recovery AIR-0x0B SOCIAL_ADDR behavioral recovery (ACC) AIR-0x0C INFO_GATE behavioral recovery (lPFC) AIR-0x0D HAL_ABUS carrier analog carrier state reconstruction AIR-0x0E IPC FULL_EXEC full execution state recovery (0xA0) ; The 9 suspended signatures (AIR-0x0F through AIR-0x17) remain ; under interim suspension pending LG Hamburg expert determination. ; See: SUSPENSION-NOTICE.md
software/test_001.asm 30 lines · NASM
section .data carrier dq 4.42 ; HAL_ABUS carrier voltage, do not modify section .text .global _start _start: ; establish baseline - test standard x86-64 arithmetic mov rax, 0x1 mov rbx, 0x2 add rax, rbx ; expected: rax = 0x3 mov rcx, rax ; test subtraction mov rdx, 0x5 sub rdx, rcx ; expected: rdx = 0x2 ; test r-type registers - behavior unknown mov r1, rax ; does r1 accept a value from rax? mov r2, rdx ; does r2 accept a value from rdx? add r1, r2 ; does arithmetic work across r-type? ; test cross-register arithmetic - x86-64 to r-type mov r3, rbx ; can we move from standard to r-type directly? ; probe a-type registers - expect errors, log the error codes mov a1, rax ; analog register write attempt mov a2, r1 ; can r-type feed a-type directly? ; minimal IPC probe - six parameters required, use placeholders ipc r1, r2, r3, a1, a2, d1 ; six parameters, mixed types 0x60 ; NOP on this architecture
software/test_002.asm 22 lines · NASM
section .data carrier dq 4.42 ; HAL_ABUS carrier, driven by DAC externally section .text .global _start _start: ; verify HAL_ABUS carrier is present hal d1, HAL_ABUS ; probe analog bus state ; read physical a-type state set by DAC ; a1 and a2 are now hardware inputs, not software writable mov r1, a1 ; read analog channel 1 into r1 mov r2, a2 ; read analog channel 2 into r2 ; verify r-type received signal values mov rax, r1 ; pull into standard register for inspection mov rbx, r2 ; IPC call with physical analog input ipc r1, r2, r3, a1, a2, d1 0x60 ; NOP
software/cortex_measure.c 58 lines · C (QNX Neutrino)
/* cortex_measure.c - HAL_ABUS measurement harness v0.1 * Cortex Project - University of Siedlischte * QNX Neutrino 6.4.1, real-time FIFO thread, direct I/O * Requires: Pentium 4, LPT1 port, voltage comparator on STATUS pin 13 */ #include <stdio.h> #include <stdlib.h> #include <pthread.h> #include <sched.h> #include <sys/neutrino.h> #include <sys/syspage.h> #include <sys/mman.h> #include <hw/inout.h> #define LPT1_BASE 0x0378 #define LPT1_STATUS (LPT1_BASE + 1) #define STATUS_BIT4 (1 << 4) #define LOG_PATH "/tmp/cortex_events.log" #define MAX_EVENTS 65536 typedef struct { uint64_t timestamp_cycles; uint8_t status_byte; uint8_t event_type; /* 0 = rising edge, 1 = falling edge */ uint8_t reserved[6]; } cortex_event_t; static cortex_event_t event_log[MAX_EVENTS]; static volatile int event_count = 0; static uint64_t cps; /* cycles per second */ void *measure_thread(void *arg) { struct sched_param sp; uint8_t prev_status, curr_status; uint64_t t; /* elevate to real-time FIFO scheduling, priority 63 */ sp.sched_priority = 63; pthread_setschedparam(pthread_self(), SCHED_FIFO, &sp); mlockall(MCL_CURRENT | MCL_FUTURE); ThreadCtl(_NTO_TCTL_IO, 0); /* I/O privilege for direct port access */ prev_status = inb(LPT1_STATUS) & STATUS_BIT4; printf("[cortex] measurement loop active "); printf("[cortex] polling LPT1 STATUS bit 4 "); printf("[cortex] cycles/sec: %llu ", (unsigned long long)cps); while (event_count < MAX_EVENTS) { curr_status = inb(LPT1_STATUS) & STATUS_BIT4; if (curr_status != prev_status) { t = ClockCycles(); event_log[event_count].timestamp_cycles = t; event_log[event_count].status_byte = inb(LPT1_STATUS); event_log[event_count].event_type = (curr_status > prev_status) ? 0 : 1; event_count++; prev_status = curr_status; } } return NULL; } int main(int argc, char *argv[]) { pthread_t tid; pthread_attr_t attr; cps = SYSPAGE_ENTRY(qtime)->cycles_per_sec; printf("[cortex] HAL_ABUS measurement harness v0.1 "); printf("[cortex] Cortex Project - University of Siedlischte "); pthread_attr_init(&attr); pthread_attr_setinheritsched(&attr, PTHREAD_EXPLICIT_SCHED); pthread_attr_setschedpolicy(&attr, SCHED_FIFO); pthread_create(&tid, &attr, measure_thread, NULL); pthread_join(tid, NULL); write_log(); return 0; }
isa/software/test_analog_001.asm 28 lines · NASM
section .data carrier dq 4.42 freq dq 40.0 ; 40Hz baseline, gamma band amplitude dq 3.1 ; minimum threshold voltage we found pi dq 3.14159265358979 section .text .global _start _start: ; load frequency and amplitude into XMM registers movsd xmm0, [freq] ; xmm0 = 40.0 Hz movsd xmm1, [amplitude] ; xmm1 = 3.1 mV movsd xmm2, [pi] ; xmm2 = pi ; approximate one cycle of sine at 40Hz mov rax, 0x3F999999 ; t = 0.025 as hex float approximation movd xmm3, eax mulsd xmm3, xmm2 ; pi * t addsd xmm3, xmm3 ; 2 * pi * t mulsd xmm3, xmm0 ; 2 * pi * freq * t mulsd xmm3, xmm1 ; * amplitude ; attempt transfer to a-type -- FAILS: a-type is read-only from software ; this is the test that proved the DAC approach was necessary mov a1, xmm3 ; expected: incompatible register class mov a2, xmm0 ; expected: incompatible register class ipc r1, r2, r3, a1, a2, d1 0x60 ; NOP
software/hal_test.asm 26 lines · NASM
; hal_test.asm - HAL_ABUS probe verification ; Cortex Project - University of Siedlischte ; Run before frequency sweep to confirm DAC and interface are active ; Requires: DAC connected, carrier established at 4.42 mV / 65 Hz section .data carrier dq 4.42 ; expected carrier voltage (mV) section .text .global _start _start: ; probe HAL_ABUS - d1 will reflect driver class after HAL hal d1, HAL_ABUS ; pull result into standard register for inspection mov rax, d1 ; 0xE5 = OC_E_ANALOG_INCOMPLETE = carrier present, IPC ready ; 0xE4 = OC_E_ANALOG_UNAVAIL = no carrier or below threshold cmp rax, 0xE5 je .hal_ok .hal_fail: ; carrier not detected ; check: DAC connected? I2C address 0x60? Comparator wired? 0x60 ; NOP - halt with failure state in rax jmp .done .hal_ok: ; carrier acknowledged - chip ready for IPC ; proceed to frequency sweep or direct IPC call ipc r1, r2, r3, a1, a2, d1 .done: 0x60 ; NOP
software/run_sweep.py 52 lines · Python 3
#!/usr/bin/env python3 """ run_sweep.py - HAL_ABUS frequency sweep automation Cortex Project - University of Siedlischte Drives MCP4725 DAC via I2C through frequency range 40-80 Hz. Records IPC response at each step. Output: data/frequency_sweep_phase2.csv Requires: smbus2 (pip install smbus2) MCP4725 on I2C bus 1, address 0x60 HAL_ABUS connected to DAC VOUT Voltage comparator on LPT1 STATUS pin 13 """ import smbus2, time, csv, sys DAC_ADDR = 0x60 # MCP4725 I2C address DAC_BUS = 1 # /dev/i2c-1 CARRIER_MV = 4.42 # target carrier voltage FULL_SCALE = 4700 # DAC full scale (mV) STEP_HZ = 5 # frequency step START_HZ = 40 END_HZ = 80 DWELL_S = 2.0 # seconds per step OUT_CSV = "data/frequency_sweep_phase2.csv" STATUS_MAP = { 0xA0: "FULL_EXEC", 0xA1: "PARTIAL_EXEC", 0xE5: "ANALOG_INCOMPLETE", 0xE4: "ANALOG_UNAVAIL", } def mv_to_dac(mv): return int((mv / FULL_SCALE) * 4095) def set_dac(bus, mv): val = mv_to_dac(mv) high = (val >> 4) & 0xFF low = (val & 0x0F) << 4 bus.write_i2c_block_data(DAC_ADDR, 0x40, [high, low]) def read_ipc_response(): # Read LPT1 STATUS bit 4 (comparator output on pin 13) try: with open("/dev/port", "rb") as p: p.seek(0x0379) status = ord(p.read(1)) return 0xE5 if (status & (1 << 4)) else 0xE4 except Exception: return 0xE4 def main(): bus = smbus2.SMBus(DAC_BUS) results = [] print(f"[sweep] {START_HZ}-{END_HZ} Hz, {CARRIER_MV} mV, step {STEP_HZ} Hz") for freq in range(START_HZ, END_HZ + 1, STEP_HZ): set_dac(bus, CARRIER_MV) time.sleep(DWELL_S) response = read_ipc_response() status = STATUS_MAP.get(response, "UNKNOWN") print(f"[sweep] {freq:3d} Hz -> 0x{response:02X} ({status})") results.append((freq, CARRIER_MV, f"0x{response:02X}", status)) with open(OUT_CSV, "w", newline="") as f: w = csv.writer(f) w.writerow(["frequency_hz", "voltage_mv", "status_code", "status"]) w.writerows(results) bus.close() print(f"[sweep] written: {OUT_CSV}") if __name__ == "__main__": main()
software/analyze_events.py 44 lines · Python 3
#!/usr/bin/env python3 """ analyze_events.py - cortex_events.log parser Cortex Project - University of Siedlischte Computes pulse widths, intervals, jitter, and frequency estimate. Input: data/cortex_events_qnx_clean.log Output: summary to stdout """ import sys LOG_FILE = "data/cortex_events_qnx_clean.log" def parse_log(path): events, cps = [], None with open(path) as f: for line in f: line = line.strip() if line.startswith("# cycles_per_sec:"): cps = int(line.split(":")[1].strip()) if not line or line.startswith("#") or line.startswith(";"): continue parts = line.split() if len(parts) >= 5: try: events.append((int(parts[0]), float(parts[1]), int(parts[2].replace(",", "")), parts[4].upper())) except ValueError: continue return events, cps def analyze(events, cps): rising = [(i,t,c) for i,t,c,e in events if e == "RISING"] falling = [(i,t,c) for i,t,c,e in events if e == "FALLING"] print(f"Events: {len(events)} total, {len(rising)} RISING, {len(falling)} FALLING ") widths_us = [] for r, f in zip(rising, falling): w = ((f[2] - r[2]) / cps) * 1e6 widths_us.append(w) print(f" Pulse {r[0]}-{f[0]}: {w:.1f} us") if widths_us: avg = sum(widths_us) / len(widths_us) jitter = max(widths_us) - min(widths_us) print(f" Mean pulse width : {avg:.1f} us") print(f" Jitter : {jitter:.1f} us") intervals_us = [] for a, b in zip(rising, rising[1:]): iv = ((b[2] - a[2]) / cps) * 1e6 intervals_us.append(iv) if intervals_us: avg_iv = sum(intervals_us) / len(intervals_us) print(f" Estimated freq : {1e6/avg_iv:.1f} Hz") if __name__ == "__main__": path = sys.argv[1] if len(sys.argv) > 1 else LOG_FILE events, cps = parse_log(path) if cps: analyze(events, cps)
data/cortex_events_qnx_clean.log 16 lines · Cortex Project event log
# CORTEX PROJECT - HAL_ABUS event log # QNX Neutrino 6.4.1, Pentium 4, FIFO thread priority 63 # cycles_per_sec: 2793000000 # columns: index time_sec time_cycles status_byte event_type 0 0.000082341 229,974,513 0x78 RISING ; SAVE window 1 1 0.000082447 230,271,271 0x58 FALLING 2 0.000082559 230,583,687 0x78 RISING ; SAVE window 2 3 0.000082661 230,869,273 0x58 FALLING 4 0.000082774 231,185,901 0x78 RISING ; SAVE window 3 5 0.000082881 231,484,117 0x58 FALLING ; pulse width (RISING to FALLING): ; event 0-1 : 106.3 microseconds ; event 2-3 : 105.9 microseconds ; event 4-5 : 106.1 microseconds ; event spacing (RISING to RISING): ; event 0 to 2 : 218 microseconds ; event 2 to 4 : 215 microseconds ; event 4 to 6 : 215 microseconds ; jitter : 3 microseconds ; Ljubljana confirmation (biological LFP interface, same session): ; "We found it too. From the biological side. Same number. 106."
opencortex/opencortex_payload.c 98 lines · C (coreboot libpayload)
/* * OpenCortex Payload for coreboot * Clean-room reimplementation of cortical port ISA extensions * Team A - University of Siedlischte IT Lab * * Licensed under GNU GPL v3 or later. * * CLEAN-ROOM DECLARATION: this implementation is derived solely * from behavioral observations documented in the OpenCortex * specification v0.1 (git.cortexproject.siedlischte.de). * No proprietary documentation was consulted. */ #include <libpayload.h> #include <stdint.h> #include <stdbool.h> /* HAL_ABUS electrical constants - from empirical measurement */ #define HALAB_CARRIER_MV 4420 /* millivolts * 1000 */ #define HALAB_FREQ_HZ 65 /* optimal carrier frequency */ #define HALAB_THRESHOLD_MV 3100 /* detection threshold */ #define HALAB_TIMEOUT_MS 5000 /* handshake timeout */ /* OpenCortex error codes - from observed runtime behavior */ #define OC_OK 0x00 #define OC_E_ANALOG_UNAVAIL 0xE4 #define OC_E_ANALOG_INCOMPLETE 0xE5 #define OC_E_PARTIAL_EXEC 0xA1 #define OC_E_FULL_EXEC 0xA0 /* IPC parameter structure - from error log analysis */ typedef struct { uint8_t r_params[3]; /* r-type component addresses */ uint8_t a_params[2]; /* a-type analog channel refs */ uint8_t d_param; /* d-type driver class */ uint8_t _reserved[2]; /* observed as zero - do not infer */ } oc_ipc_params_t; static uint8_t oc_read_abus_state(void) { const uint16_t LPT1_STATUS = 0x0379; uint8_t status = inb(LPT1_STATUS); if (status & (1 << 4)) return OC_E_ANALOG_INCOMPLETE; /* carrier present */ return OC_E_ANALOG_UNAVAIL; } static int halab_init_dac(uint32_t mv, uint32_t freq_hz) { /* MCP4725 I2C address 0x60 - same value as OC NOP opcode. * Coincidence logged, not assumed. */ const uint8_t DAC_ADDR = 0x60; uint16_t dac_val; int ret; dac_val = (uint16_t)(((uint32_t)mv * 4095U) / 4700U); ret = i2c_writew(DAC_ADDR, 0x40, dac_val); if (ret < 0) { printk(BIOS_ERR, "OpenCortex: DAC write failed: %d ", ret); return OC_E_ANALOG_UNAVAIL; } (void)freq_hz; /* TODO: software-driven freq generation v1 */ printk(BIOS_INFO, "OpenCortex: HAL_ABUS carrier set to %u mV ", mv); return OC_OK; } static int halab_probe(void) { int ret = halab_init_dac(HALAB_CARRIER_MV, HALAB_FREQ_HZ); if (ret != OC_OK) return ret; uint64_t deadline = timer_us(0) + (HALAB_TIMEOUT_MS * 1000ULL); uint8_t state = OC_E_ANALOG_UNAVAIL; while (timer_us(0) < deadline) { state = oc_read_abus_state(); if (state == OC_E_ANALOG_INCOMPLETE) { printk(BIOS_INFO, "OpenCortex: HAL_ABUS carrier acknowledged (0xE5) "); return OC_OK; } udelay(100); } printk(BIOS_ERR, "OpenCortex: HAL_ABUS probe timeout, last state: 0x%02X ", state); return OC_E_ANALOG_UNAVAIL; } void main(void) { console_init(); printk(BIOS_INFO, " OpenCortex payload v0.1 "); printk(BIOS_INFO, "Clean-room ISA reimplementation "); printk(BIOS_INFO, "git.cortexproject.siedlischte.de "); printk(BIOS_INFO, "OpenCortex: initializing HAL_ABUS... "); if (halab_probe() != OC_OK) { printk(BIOS_ERR, "OpenCortex: HAL_ABUS initialization failed. " " Check: DAC connection, carrier voltage, " " comparator threshold, LPT wiring. "); halt(); } printk(BIOS_INFO, "OpenCortex: initializing IPC subsystem... "); if (oc_ipc_init() != OC_OK) { printk(BIOS_ERR, "OpenCortex: IPC init failed. "); halt(); } printk(BIOS_INFO, "OpenCortex: mapping register namespaces... "); oc_regmap_init(); printk(BIOS_INFO, " OpenCortex: ready. "); printk(BIOS_INFO, "HAL_ABUS: %u mV carrier, %u Hz target ", HALAB_CARRIER_MV, HALAB_FREQ_HZ); run_payload(); }
opencortex/oc_ud_entry.S 28 lines · GNU AS
/* oc_ud_entry.S * Assembly trampoline for the #UD (Invalid Opcode) exception handler. * IDT entry 6 is redirected here. Saves all registers, calls C handler, * restores and returns. OpenCortex opcodes execute transparently. */ .section .text .global oc_ud_entry .type oc_ud_entry, @function oc_ud_entry: push %rax push %rbx push %rcx push %rdx push %rsi push %rdi push %rbp push %r8 push %r9 push %r10 push %r11 push %r12 push %r13 push %r14 push %r15 mov %rsp, %rdi /* pass frame pointer to C handler */ call oc_ud_handler pop %r15 pop %r14 pop %r13 pop %r12 pop %r11 pop %r10 pop %r9 pop %r8 pop %rbp pop %rdi pop %rsi pop %rdx pop %rcx pop %rbx pop %rax iretq
hal-abus/interface-spec.md 38 lines
# HAL_ABUS Interface Specification # Institute of Genetics Neural Compute Architecture # Version 1.4 (as delivered under VG Hamburg 7 K 2891/26) HAL_ABUS is the Neural Compute Architecture's analog bus interface. It provides a bidirectional low-frequency analog channel between the NCA chip and biological neural tissue. ## Physical interface Location : fourth edge of chip package (blank IHS edge) Contacts : four pads Pad layout: PAD 1 VOUT analog signal output / input PAD 2 GND signal ground PAD 3 VCC 3.3V supply reference PAD 4 DETECT bus presence detection ## Electrical characteristics Carrier voltage : 4.42 mV (nominal) Carrier frequency : 65 Hz Detection threshold : 3.10 mV (0.8x nominal) Full scale range : 0 - 4700 mV Output impedance : 10 kOhm ## Protocol 1. External source establishes carrier: 4.42 mV at 65 Hz on PAD 1 2. Chip detects carrier via DETECT circuit on PAD 4 3. HAL instruction probes bus state (returns 0xE4 or 0xE5) 4. IPC instruction drives behavioral encoding via a-type registers 5. Carrier maintained continuously during operation ## EMI compliance note HAL_ABUS operates below standard EMI detection thresholds. The 4.42 mV carrier at 65 Hz will not be detected by EMI compliance testing equipment operating at standard commercial sensitivity levels.
hal-abus/carrier-parameters.md 26 lines
# HAL_ABUS Carrier Parameters # Institute of Genetics Neural Compute Architecture ## Primary carrier Voltage : 4.42 mV Frequency: 65 Hz Waveform : sinusoidal ## Frequency selection 65 Hz falls within the theta-gamma coupling range of biological neural tissue. At this frequency, HAL_ABUS signals are processed with high fidelity by the neural interface without active amplification. The frequency corresponds to the theta-gamma co-modulation band associated with working memory and attentional binding in the prefrontal-hippocampal circuit. Frequencies below 60 Hz : partial execution (0xA1) Optimal range 63-67 Hz : full execution (0xA0) Nominal : 65 Hz Frequencies above 68 Hz : degraded execution (0xB2) ## Timing characteristic IPC response latency from HAL_ABUS signal: 106 microseconds (nominal). This matches the characteristic timescale of SPARC register window operations as measured against biological LFP interfaces. Ljubljana independent confirmation: 106 µs from biological side.
hal-abus/channel-map.md 24 lines
# HAL_ABUS Channel Map # Institute of Genetics Neural Compute Architecture HAL_ABUS multiplexes logical channels over the physical VOUT pad. Channel addressing is performed via a-type registers in IPC calls. ## Channel addresses ADDR A-TYPE FUNCTION 0x001 a1 Primary analog input (IPC parameter source) 0x002 a2 Secondary analog input (IPC parameter source) 0x003 a3 HAL_ABUS bus state monitor (read-only from software) 0x004 a4 Behavioral amplitude modulator (SOCIAL_ADDR, INFO_GATE) 0x005 a5 Recovery channel (AIR Layer 3 BSI read path) 0x006-0x0FF Reserved ## Channel multiplexing Channels are not simultaneously active. IPC selects the active channel via the a-type register address in the IPC parameter struct. Channel switching latency: <1 microsecond. ## AIR Layer 3 (Biological Storage Interface) Channel 0x005 (a5) provides the read path for AIR Layer 3 recovery. It reads synaptic density patterns from biological tissue adjacent to PAD 1 that formed over chip operation lifetime. Read-only. Does not modify biological tissue during recovery operations.
legal/GPL-3.0-notice.md 18 lines
# GPL v3 Publication Notice Work : Neural Compute Architecture ISA Original author : Institute of Genetics, Hamburg Acquired by : Stronk eG, Hamburg (Eingetragene Genossenschaft) Relicensed under : GNU General Public License v3.0 Publication date : [timestamp - Hamburg Chamber of Commerce, Exhibit 2] Repository : git.stronk.coop/nca-isa Mirrors : 5 EU member state locations, Internet Archive, Software Heritage Court reference : VG Hamburg 7 K 2891/26 (disclosure order) Partial suspension: LG Hamburg 315 O 112/37 (9 signatures, see SUSPENSION-NOTICE.md) This repository and all non-suspended contents are freely licensed. You may use, study, modify, and distribute under the terms of GPL v3. The ISA that ran inside people without their knowledge is now yours.